SEMINARS
MeetingThe Multi-GB/s Challenges With Signal Integrity Design
Signal integrity (SI) analysis has traditionally been used as a verification step prior to releasing a design for manufacturing. This methodology has served the high-speed design community well, even as clock frequencies and data rates push through 100 MHz and near 1 GHz..
Today's next-generation communications designs, however, are now reaching data rates up to 3-5 GB/s and beyond. Fundamental assumptions that have enabled "fixing up" the "timing" at the end of the design cycle are no longer viable. High-speed signal paths are now often the critical path for product development and a new, more proactive approach is needed.
Using the Xilinx Virtex 4 Rocket I/O as an example, this seminar outlines a modern SI design methodology that utilizes a top-down approach to IC, packaging, and PCB SI. This approach solves many SI issues early in the design phase, prior to analysis, thereby saving design iterations and shortening time-to-manufacture.
Please, go to http://seminar2.techonline.com/s/awr_oct0306 to view the AWR/Synopsys SI NetSeminar.